`timescale 1ns/1ns

module JC_counter(
           input clk,
           input rst_n,
           output reg [3: 0] Q
       );

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			Q <= 4'd0;
		else if (Q % 2 == 1'b0)
			Q <= {1'b1, Q[3: 1]};
		else if (Q % 2 == 1'b1)
			Q <= {1'b0, Q[3: 1]};
	end

endmodule
